1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a dual damascene process in which a contact and a metal wiring are formed in a trench and a via hole, respectively.
2. Description of the Related Art
For some time now, semiconductor devices have been employed in most electronic devices including not only information processing apparatuses but also home appliances. For an information processing apparatus such as a computer, our technological society requires that the apparatus develop a larger processing capacity and a more rapid processing speed. Thus, the semiconductor device installed in the information processing apparatus is also required to have a rapid response speed and large storage capacity. This is achieved through a high integration level of the semiconductor device.
In general, the storage capacity of a random access memory (RAM) chip can be expressed by using the empirically obtained Moores' law that indicates a general development rate of a memory chip. According to Moores' law, the storage capacity of a memory chip increases by a factor of four every three years. This increase is accomplished through a combination of reducing the size of the semiconductor device and increasing the length of a silicon chip in accordance with the size reduction of the semiconductor device. As the size of the semiconductor device installed on the silicon chip is reduced, interconnect lines of the semiconductor device are also diminished. When the interconnect lines are closely arranged, however, the interconnect lines interfere with each other. In cases where the interval between the interconnect lines is below a predetermined value, the signal delay in the device is caused entirely by the interference between the interconnect lines. To subsequently increase the processing speed of the semiconductor device in this situation, the specific resistance in the metal used for forming the interconnect lines must be reduced.
Until recently, the interconnect lines of the semiconductor device were formed using aluminum (Al) or aluminum alloy having the specific resistance of approximately 2.66 μΩ·cm. However, since International Business Machine Co. disclosed a method for forming an interconnect line with copper (Cu) in 1998, various researchers have progressed and improved the methods for forming interconnect lines or wiring using copper. Conventional photolithography processes are rarely used for forming interconnect lines or wiring with copper because the copper is too rapidly diffused in most metal films. Thus, a damascene process was developed in order to form the copper interconnection line or the copper wiring. In fact, a dual damascene process is often advantageously employed because the metal wiring and a contact can be simultaneously formed in one process.
U.S. Pat. No. 5,935,762 (issued to Chang-Ming Dai), Korean Laid Open Patent Publication No. 2002-66567, and Korean Laid Open Patent Publication No. 2002-55889 disclose methods for manufacturing a semiconductor device with copper interconnection lines using a dual damascene process.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1A, a first insulation film 15 including a groove or a trench is formed on a semiconductor substrate 10. A conductive pattern 20 is formed in the groove or the trench, and the upper face of the conductive pattern 20 is exposed.
After a barrier layer 25 is formed on the first insulation film 15 and the conductive pattern 20, a second insulation film 30 and a third insulation film 35 are successively formed on the barrier film 25. The third insulation film 35 includes material having a dielectric constant below approximately 3.5.
A via hole is formed through the second insulation film 30 in order to form a contact electrically connecting the conductive pattern 20 to a metal wiring that is successively formed. The second insulation film 30 electrically isolates adjacent contacts formed in adjacent via holes from each other. Meanwhile, a trench is formed through the third insulation film 35, and the metal wiring is formed in the trench. The third insulation film 35 electrically isolates adjacent metal wirings formed in adjacent trenches from each other. To accomplish this purpose, the third insulation film 35 includes a low dielectric material having carbon (C) or oxygen (O2) so as to prevent the increase in the capacitance between the adjacent metal wirings.
Referring to FIG. 1B, after a first photoresist film (not shown) is coated on the third insulation film 35, the first photoresist film is patterned to form a first photoresist pattern 40 for the formation of the via hole 45 through the second insulation film 30.
Subsequently, portions of the third and second insulation films 35 and 30 are etched using the first photoresist pattern 40 as an etching mask until a portion of the barrier layer 25 positioned on the conductive pattern 20 is exposed. Thus, the via hole 45 is formed through the second insulation film 30. Next, the first photoresist pattern 40 is removed.
Referring to FIG. 1C, a second photoresist film 50 is coated on the third insulation film 35 to fill up the via hole 45 by a spin coating process. The overall thickness Tpr of the second photoresist film 50 becomes very thick because the second photoresist film 50 fills up the via hole 45 formed through the second and the third insulation films 30 and 35.
Referring to FIG. 1D, the second photoresist film 50 is patterned to form a second photoresist pattern 55 for forming the trench by a photolithography process.
Subsequently, the third insulation film 35 is partially etched using the second photoresist pattern 55 as an etching mask so that the trench 60 having a line shape that is partially connected to the via hole 45 is formed through the third insulation film 35. The trench 60 is where the metal wiring will be located, and it has a size wider than that of the via hole 45. Next, the barrier layer 15 is partially etched, thereby exposing the conductive pattern 20 in the first insulation film 15.
Referring to FIG. 1E, after the second photoresist pattern 55 is removed, the via hole 45 and the trench 60 is filled by a copper (Cu) film formed by a sputtering process, a chemical vapor deposition process, or an electro plating process. Then, the copper film is polished through a chemical-mechanical polishing (CMP) process. Thus, metal wiring 70 and a contact 65 electrically connected to the conductive pattern 20 are formed in the trench 60 and via hole 45 (FIG. 1D), respectively.
However, in the conventional semiconductor manufacturing method using the dual damascene process, because the height of the photoresist film coated on the insulation film is exceedingly high in order to form the trench in which the metal wiring is positioned, the deep of focus (DOF) of the photolithography process may not be sufficiently ensured when the photoresist film is patterned with the photolithography process. As a result, the photoresist pattern formed from the photoresist film may not have a desired shape and dimension. That is, to form the photoresist pattern serving as an etching mask during the formation of the via hole or the trench, a photoresist film 50 having exceedingly thick thickness Tpr is coated on the insulation film 35 as shown in FIG. 1C. Hence, when the photoresist film 50 is exposed and developed to form the photoresist pattern, the margin for the DOF of the photolithography process may be reduced too much so that the DOF of the photolithography process is greatly deteriorated. The via hole or the trench may not have precise dimensions since the photoresist pattern formed under such processing condition may not have a required dimension and a precise shape. As a result, the manufacturing process yield of the semiconductor device may be reduced. When the thickness Tpr of the photoresist film is reduced, the etching durability of the photoresist pattern may be deteriorated although the DOF of the photolithography process may be improved.